1. Field of the Invention
This invention relates to a method of fabricating a semiconductor memory device. More particularly, this invention relates to a method of fabricating a semiconductor memory device which includes formation of miniature capacitors through electrode formation using a CMP method in order to achieve a high integration density in ferroelectric memories and DRAMs.
2. Description of the Related Art
FIG. 3 of the accompanying drawings illustrates a ferroelectric memory cell having one-transistor/one-capacitor (or two-transistor/two-capacitor) structure according to the prior art. A planar capacitor Cp is formed over a transistor Tr with intervention of an insulating film 30 as shown in FIG. 3. The transistor Tr and the capacitor Cp are completely isolated from each other. Therefore, after the capacitor Cp is formed on the insulating film 30, the capacitor Cp and the transistor Tr are connected by local lead wires 31.
However, the structure of the memory cell shown in FIG. 3 has a large occupying area and is not suitable for achieving high integration.
To solve this problem, a ferroelectric memory cell or a DRAM having a structure in which a contact plug 33 made of polysilicon or tungsten is formed on a source region 32 of a MOSFET and a stacked capacitor Cp is formed over the contact plug 33, has been proposed.
The stacked capacitor Cp shown in FIG. 4 is generally fabricated in the following way. A conductive film made of a material such as Ir, IrO.sub.2 /Ir, Pt, Ru or RuO.sub.2 /Ru is deposited on a semiconductor substrate including transistors, an interlayer insulating film deposited on the transistors, and contact holes each being bored in the interlayer insulating film and contact plugs each being formed inside the contact hole. The conductive film is patterned to form bottom electrode (node electrode) by dry etching. A ferroelectric film (such as PZT or SBT) or a high dielectric film (such as BST) is deposited, and a conductive film as a top electrode, made of a material such as Ir, IrO.sub.2, Pt, Ru or RuO.sub.2 is deposited. The conductive film and the ferroelectric film (or the high dielectric film) are patterned to form a common plate (or a drive line) by dry etching.
However, the conductive film of Pt, Ir, IrO.sub.2, or the like, used for the top electrode or the bottom electrode, has generally low reactivity with a halogenated gas used for dry etching, and volatility of reaction products is low, too. Therefore, its etching rate is low and fine patterning is difficult to perform. Furthermore, in the case of patterns of the order of sub-micron or finer, a micro-loading effect is serious and there arise the problems of adhesion of the reaction products to the conductive film and the development of particles.
In order to achieve a high integration density of the memories of this kind, it is essentially necessary to establish a fine etching technique for inactive metals such as Pt and Ir.
Therefore, Japanese Patent Laid-Open Nos. HEI 9(1997)148537 and HEI 7(1995)22518 propose etching-back by a chemical mechanical polishing (CMP) method using a slurry containing a strong acid or alkali electrolyte.
According to Japanese Patent Laid-Open No. HEI 9(1997)148537, for example, a SiO.sub.2 film 42 is formed on a contact plug 41 in a semiconductor substrate that includes transistors, an interlayer insulating film 40 deposited on the transistors, contact holes formed in the interlayer insulating film 40 and contact plugs formed inside the contact holes, as shown in FIG. 5. Then an opening is formed in this SiO.sub.2 film above the contact plug 41 using a mask, a bottom electrode 43, a ferroelectric member 44, a top electrode 45 and a TEOS film 46 are serially deposited into this opening. These films are then polished simultaneously by a CMP method. In consequence, an isolated capacitor Cp having a recess shape is fabricated inside the opening formed in the SiO.sub.2 film and at the same time the TEOS film 46 is buried in the recess of the surface of this isolated capacitor Cp. A contact hole is opened in the TEOS film 46 at the recess of the isolated capacitor Cp by dry etching using a mask. A metal film is formed on the capacitor inclusive of this contact hole, and patterning is conducted using this metal film as a mask in order to form a common plate electrode 47.
However, such a process requires three masks, that is, the mask for forming the opening in the SiO.sub.2 film on the contact plug 41, the mask for opening the contact hole in the TEOS film 46 and the mask for patterning to form the common plate electrode 47. In addition, such a process requires the CMP method for forming the capacitor inside the opening of the SiO.sub.2 film 42 and a dry etching step for forming the contact hole in the TEOS film 46. Furthermore, the contact hole must be formed above the resulting capacitor. After all, this process involves the problem that the formation of the contact hole itself will be difficult when further miniaturization is required.
According to Japanese Patent Laid-Open No. HEI 7(1995)22518, a SiO.sub.2 film 52 is formed on a contact plug 51 in a semiconductor substrate that has transistors, an interlayer insulating film 50, contact holes formed in the interlayer insulating film 50 and the contact plugs 51 formed inside the contact holes, as shown in FIG. 6. An opening is then formed in the SiO.sub.2 film 52 above the contact plug 51 using a mask, and a conductive film is deposited on the opening. The conductive film is polished by CMP method to form an isolated storage electrode 53, that is connected to the contact plug 51. Next, a ferroelectric film 54 and a SiO.sub.2 film 55 are serially deposited on the storage electrode 53. A trench corresponding to a drive line is formed in the SiO.sub.2 film 55 above the storage electrode 53 using a mask, and a conductive film is deposited. Subsequently, the conductive film is polished by a CMP method so as to form an isolated drive line 56.
However, this process involves the problem that when the ferroelectric film is patterned, the ferroelectric film on a circuit portion around a memory array is damaged by plasma caused by dry etching. As a result ferroelectric characteristics deteriorate.